Scanning pulse generating circuit

ABSTRACT

A scanning pulse generating circuit has a multiplicity of stages constitued by first basic circuits and second basic circuits which are connected to appear alternatingly in a cascade manner. The first basic circuit is composed of three or four MOS transistors and a feedback capacitor, and includes at least a bootstrap inverter, so as to produce predetermined output pulses upon receipt of driving synchronizing pulses. The second basic circuit has the same construction as the first basic circuit except that it receives different driving synchronizing pulse from that used in the first basic circuit. The output pulses from the respective basic circuits are free from drop of voltage and fluctuation, by virtue of the bootstrap effect. In addiition, power consumption can be reduced without difficulty.

BACKGROUND OF THE INVENTION

1. Field of the Invention:

The present invention relates to a scanning pulse generating circuit composed mainly of MOS transistors and suitable for use in, for example, solid-state imaging devices.

2. Description of the Related Art:

FIG. 1A shows a known scanning pulse generating circuit which drives pixels of a solid-state imaging device. This circuit has a plurality of basic circuits each composed of a two-stage inverter comprising a first-stage inverter composed of MOS transistors Q₁₂ and Q₁₃ and a second-stage inverter composed of MOS transistors Q₁₅ and Q₁₆, and a pair of signal transmitting MOS transistors Q₁₁ and Q₁₄. The basic circuits 11₋₁, 11₋₂, 11₋₃, . . . are connected in a cascade manner and output terminals 12₋₁, 12₋₂, 12₋₃, . . . are led from the connections between adjacent stages of the cascade.

In operation, a start pulse ST (see FIG. 1B) is input to the signal transmitting transistor Q₁₁. At the same time, clock pulses φ₁₁ and φ₁₂ are input to the signal transmitting transistors Q₁₁ and Q₁₄. The start pulse ST is delayed by a time corresponding to the period of the clock pulse φ₁₂ so that output pulses V₀₁, V₀₂, V₀₃, . . . are derived from the output terminals 12₋₁, 12₋₂, 12₋₃, . . . of the basic circuits 11₋₁, 11₋₂, 11₋₃, . . . of the respective stages, as shown in FIG. 1B.

Each of the MOS transistors used in the scanning pulse generating circuit of FIG. 1A is of the N-channel type. A symbol V_(DD) repesents positive D.C. source voltage, while V_(SS) represents grounding voltage. Symbols V₁₁, V₁₂ and V₁₃ appearing in FIG. 1B represent the input voltage waveform of the first-stage inverter circuit, output voltage waveform of the first-stage inverter circuit and the input voltage waveform of the second-stage inverter circuit.

This known scanning pulse generating circuit is advantageous in that the operational margin of the scanning pulse generating circuit is high and in that the wiring interconnecting the circuit elements is suitable for attaining a higher density of the circuit arrangement. Unfortunately, however, this known scanning pulse generating circuit suffers from the following disadvantages.

(1) The voltage of the "H" level of the output signal from the basic circuit of each stage is affected by a fluctuation in the threshold voltage of the load transistor Q₁₆ incorporated in the second-stage inverter of the basic circuit of the same stage, so that the basic circuits of different stages provide different levels of output signal.

(2) The voltage of the "H" level of the output signal is considerably lowered from the level of the D.C. source voltage V_(DD).

(3) Either one of the two stages of inverter is operative to conduct the inverting operation in all the basic circuits so that electric current is continuously supplied to all basic circuits, whereby the power consumption is increased. This poses a serious problem particularly when a multiplicity of stages of basic circuit, e.g., several hundreds of stages, are employed as in the case of the scanning circuit for a solid-state imaging device.

Using Complementary MOS transistors (referred to as CMOS hereinafter), a scanning pulse generating circuit is obtainable which is capable of operating at high speed with reduced power consumption and which can produce an "H" output level which is substantially the same as the source voltage, i.e., without a substantial drop in the voltage supplied from the source.

However, production of a scanning pulse generating circuit using CMOS transistors arranged in the form of an integrated circuit inconveniently requires a specific production process for forming CMOS transistors and the production process is inevitably complicated. Preferably, the scanning pulse generating circuit is constituted solely by N-channel MOS transistors or P-channel MOS transistros depending on whether the outputs to be obtained are of positive or negative voltage.

SUMMARY OF THE INVENTION

Accordingly, an object of the present invention is to provide a scanning pulse generating circuit which can provide output voltage at a constant level without substantial voltage drop, thereby to overcome the above-described problems of the prior art.

Another object of the present invention is to provide a scanning pulse generating circuit in which the basic circuit of each stage can easily be made up of a reduced number of elements and in which the power consumption is appreciably decreased.

To these ends, according to an aspect of the present invention, there is provided a scanning pulse generating circuit comprising: (a) a plurality of first basic circuits each including: a first MOS transistor with the gate terminal thereof serving as an input terminal; a second MOS transistor connected in series to the first MOS transistor with one of the main electrodes thereof being grounded while the gate terminal thereof being capable of receiving a first synchronizing pulse; a third MOS transistor having the gate terminal thereof connected to the point of juncture between the first and second MOS transistors while one of the main electrodes thereof being connected to a power supply; a fourth MOS transistor connected in series to the third MOS transistor with one of the main electrodes thereof being grounded while the gate terminal thereof being capable of receiving a second synchronizing pulse; and a first capacitive element connected between the point of juncture between the first and second MOS transistors and the point of juncture between the third and fourth MOS transistors, the point of juncture between the third and fourth MOS transistors constituting an output terminal; and (b) a plurality of second basic circuits each including: fifth, sixth, seventh and eighth MOS transistors corresponding to the first, second, third and fourth MOS transistors of the first basic circuit, respectively; and a second capacitive element corresponding to the first capacitive element; the fifth, sixth, seventh and eighth MOS transistors and the second capacitive element being connected in the same manner as the corresponding elements in the first basic circuit, the output terminal of the first basic circuit being connected to the gate terminal of the fifth MOS transistor, the gate terminals of the sixth and eighth MOS transistors being capable of receiving third and fourth synchronizing pulses, respectively; the first and second basic circuits being connected alternatingly in a multiplicity of stages so that scanning pulses are derived from the output terminals of the basic circuits of the successive stages.

According to another aspect of the present invention, there is provided a scanning pulse generating circuit comprising: (a) a plurality of first basic circuit each including: a first MOS transistor having an input terminal constituted by one of the main electrodes thereof while the gate terminal thereof being capable of receiving a first synchronizing pulse; a second MOS transistor with the gate terminal thereof connected to the other of the main electrodes of the first MOS transistor and with one of the main electrodes thereof connected to a power supply; a third MOS transistor connected in series to the second MOS transistor with one of the main electrodes thereof being grounded while the gate terminal thereof is capable of receiving a second synchronizing pulse; and a first capacitive element connected between the gate terminal of the second MOS transistor and the point of juncture between the second and third MOS transistors, the point of juncture between the second and third MOS transistors serving as an output terminal; and (b) a plurality of second basic circuits each including: fourth, fifth and sixth MOS transistors corresponding to the first, second and third MOS transistors of the first basic circuit, respectively; and a second capacitive element corresponding to the first capacitive element of the first basic circuit; the fourth, fifth and sixth MOS transistors and the second capacitive element being connected in the same manner as the corresponding elements of the first basic circuit, the output terminal of the first basic circuit being connected to one of the main electrodes of the fourth MOS transistor, the gate terminals of the fourth and sixth MOS transistors being capable of receiving third and fourth synchronizing pulses, respectively; the first and second basic circuits being connected alternatingly in a multiplicity of stages so that scanning pulses are successively output from the output terminals of the basic circuits of the successive stages.

Thus, in the scanning pulse generating circuit according to the present invention, voltage drop is completely eliminated by virtue of the bootstrap effect which is realized by the capacitance of the capacitive element determined to be suitably greater than the parasitic capacitance. This arrangement ensures that all the basic circuits can produce "H" outputs of substantially equallevels. In addition, power consumption is remarkably reduced because only one basic circuit conducts the inverting operation at any moment. It is also to be pointed out that the pitch of arrangement of the basic circuits, i.e., the distance between adjacent basic circuits, can be reduced owing to the reduced number of elements of the basic circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a circuit diagram showing the construction of a conventional scanning pulse generating circuit;

FIG. 1B is a chart showing signal waveforms and voltage waveforms, illustrative of the operation of the scanning pulse generating circuit of FIG. 1A;

FIG. 2A is a circuit diagram showing the construction of a bootstrap type inverter incorporated in the scanning pulse generating circuit according to the present invention;

FIG. 2B is a voltage waveform chart illustrative of the operation of the bootstrap type inverter shown in FIG. 2A;

FIG. 3A is a circuit diagram showing the construction of a first embodiment of the scanning pulse generating circuit in accordance with the present invention;

FIG. 3B is a chart showing signal waveforms and voltage waveforms illustrative of the operation of the embodiment shown in FIG. 3A;

FIG. 4 is a diagram showing the construction of a second embodiment of the present invention;

FIG. 5A is a circuit diagram showing the construction of a third embodiment of the scanning pulse generating circuit in accordance with the present invention; and

FIG. 5B is a chart showing signal waveforms and voltage waveforms illustrative of the operation of the embodiment shown in FIG. 5A.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Before commencing the description of embodiments, a description will be made of the principle of a bootstrap type inverter employed in the scanning pulse generating circuit according to the present invention. Referring to FIG. 2A, which is a circuit diagram illustrating the bootstrap type inverter comprising N-channel MOS transistors, the gate terminal of a driver transistor Q₁ serves as an input terminal 1, while the source terminal of this transistor is connected to a grounding terminal. A load transistor Q₂ connected in series to the driver transistor Q₁ has a drain terminal which is supplied with a source voltage V_(DD). An output terminal 2 is led from the juncture between both transistors Q₁ and Q₂. A third transistor Q₃ is connected between the gate terminal and the drain terminal of the load transistor Q₂. A feedback capacitor C₁ is connected between the gate terminal and the source terminal of the load transistor Q₂.

The third transistor Q₃ cooperates with the feedback capacitor C₁ so as to boost the voltage at the point 3 of juncture between the feedback capacitor C₁ and the load transistor Q₂, i.e., the voltage V₀ at the gate terminal of the load transistor Q₂. Parasitic capacitance at the juncture point 3 with respect to the ground potential is represented by C₂.

The capacitance of the feedback capacitor C₁ is so determined that the parasitic capacitance C₂ and the capacitance of the feedback capacitor C₁ normally meet the condition of C₁ /(C₁ +C₂)>about 0.6. The parasitic capacitance at the output terminal 2 is represented by C_(L).

The operation of the bootstrap type inverter will be described with reference to FIG. 2B which shows waveforms of voltages at the input terminal 1, output terminal 2 and the juncture point 3. At a moment t₁, the input voltage V_(in) at the input terminal 1 takes the "H" level. In this state, the voltage V₀ at the juncture point 3 is determined by the following formula (1) and is lower than the source voltage V_(DD).

    V.sub.0 (t.sub.1)=V.sub.DD -V.sub.T -ΔV.sub.T        (1)

In this formula (1), a symbol V_(T) represents the threshold voltage of the MOS transistor, while ΔV_(T) is given by the following equation. ##EQU1## where, K is a value given by: ##EQU2## wherein, φ_(F) : Fermi potential of the transistor substrate or P-type well

N_(A) : acceptor density of substrate

ε₀ : dielectric constant of vacuum

K_(s) : specific dielectric constant of substrate

C_(ox) : electrostatic capacitance of gate oxide film

Meanwhile, the voltage V_(out) (t₁) at the output terminal 2 is at the "L" level which is almost equal to zero as determined by the following formula (2).

    V.sub.out (t.sub.1)≃[g.sub.m (Q.sub.2)/g.sub.m (Q.sub.1)]×V.sub.DD (<V.sub.T)                      (2)

Symbols g_(m) (Q₁) and g_(m) (Q₂) represent conductance values of the transistors Q₁ and Q₂.

When the input voltage V_(in) is lowered to the "L" level, the driver transistor Q₁ cuts off so that the output terminal voltage V_(OUT) starts to rise because of the operation of the load transistor Q₂ which is always conductive. Simultaneously, the voltage V₀ at the juncture point 3 also rises due to the capacitive couping of the feedback capacitor C₁ to satisfy the condition of V₀ >V_(DD) thereby switching off the enhancement type transistor Q₃, so that the voltage V₀ continues to rise until the voltage increment ΔV₀ reaches a value which is given by the following formula (3).

    ΔV.sub.0 =[C.sub.1 /(C.sub.1 +C.sub.2)]·[V.sub.OUT (t.sub.2)-V.sub.OUT (t.sub.1)]                            (3)

where, V_(out) (t₂) represents the voltage of the "H" level output obtained at a moment t₂.

If the capacitance of the feedback capacitor C₁ is determined to be suitably greater than the parasitic capacitance C₂, the condition expressed by the following formula (4) is satisfied.

    V.sub.0 (t.sub.2)-V.sub.T -ΔV.sub.T (V.sub.0 (t.sub.2))<V.sub.DD (4)

When the condition of formula (4) is met, the load MOS transistor Q₂ operates in unsaturated condition so that it directly transmits the drain voltage V_(DD) to the source terminal, so that the output terminal voltage V_(OUT) (t₂) derived from the source terminal becomes equal to the source voltage V_(DD).

A description will be given hereinunder as to shift-register type scanning pulse generating circuits embodying the present invention and incorporating the operation principle of the bootstrap type inverter described hereinabove.

Referring to FIG. 3A showing the circuit of a first embodiment, the basic circuit 21₋₁ of a first stage has four MOS transistors Q_(D1), Q_(L1), Q_(B1) and Q_(R1) and a capacitor C_(F). The MOS transistors Q_(D1), Q_(L1) and Q_(B1) perform operations equivalent to the operation performed by the MOS transistors Q₁, Q₂ and Q₃ of the bootstrap inverter shown in FIG. 2A. First and second MOS transistors Q_(D1) and Q_(L1), which are connected in series, constitute an inverter circuit in which the second transistor Q_(L1) serves as the load transistor while the first transistor Q_(D1) functions as the driver transistor. This inverter circuit is connected between the power supply V_(DD) and the earth terminal.

The capacitor C_(F) is composed of a MOS diode and corresponds to the feedback capacitor C₁ in the bootstrap inverter shown in FIG. 2A. This capacitor C_(F) is connected between the juncture point between the MOS transistors Q_(D1) and Q_(L1) and the gate terminal of the MOS trtansistor Q_(L1). A symbol C_(S) represents the parasitic capacitance corresponding to C₂ of the bootstrap inverter shown in FIG. 2A. A fourth MOS transistor Q_(R1) is used as a resetting transistor and is connected between the earth terminal and the source terminal of the third MOS transistor Q_(B1) which functions as a biasing transistor. The source terminal of the third MOS transistor Q_(B1) is connected to the gate terminal of the load transistor Q_(L1).

The gate terminal of the third MOS transistor Q_(B1) receives the start pulse ST, while the gate terminals of the driver transistor Q_(D1) and the fourth MOS transistor Q_(R1) receive, respectively, synchronizing pulses φ₂ and φ₄.

An output terminal 22₋₁ is led from the point of juncture between the MOS transistors Q_(D1) and Q_(L1) which constitute the inverter circuit.

A basic circuit 21₋₂ of the second stage has a construction identical to that of the basic circuit 21₋₁ of the first stage, except that it receives different synchronizing pulses. Namely, the basic circuit 21₋₂ of the second stage has MOS transistors Q_(L2), Q_(D2), Q_(B2) and Q_(R2), which correspond to the MOS transistors Q_(L1), Q_(D1), Q_(B1) and Q_(R1), and a feedback capacitor C_(F) and a parasitic capacitance C_(S). The output terminal 22₋₁ of the basic circuit of the first stage is connected to the gate terminal of the MOS transistor Q_(B2) so that the output from the basic circuit 21₋₁ of the first stage is input to the basic circuit 21₋₂ of the second stage. The gate terminals of the driver transistors Q_(D2) and the fourth MOS transistor Q_(R2) receive synchronizing pulses φ₁ and φ₃, respectively. The basic circuits 21₋₁ and 21₋₂ of the first and second stages having the described constructions are connected alternately in a cascade-like manner so as to constitute a scanning pulse circuit.

The operation of this scanning pulse generating circuit will be described with reference to FIG. 3B which illustrates waveforms of pulses applied to various portions of the circuit shown in FIG. 3A and the waveforms of voltages obtained at the respective juncture points and output terminals. The description will be made on the assumption that all the MOS transistors are of the N-channel type.

At a moment t₁, the start pulse ST applied to the gate terminal of the third MOS transistor Q_(B1) of the first stage basic circuit 21₋₁ is changed to "H" level, so that the voltage V₁ at the source terminal of the transistor Q_(B1) rises to V_(A) as a result of supply of the drain current. The conductance values g_(m) (Q_(L1)) and g_(m) (Q_(D1)) of the MOS type transistors Q_(L1) and Q_(D1) are determined beforehand so as to meet the following condition.

    [g.sub.m (Q.sub.L1)/g.sub.m (Q.sub.D1)]·V.sub.DD <V.sub.t (5)

where, V_(T) represents the threshold voltage of the MOS transistor.

Under the condition described, the voltage V₀₁ obtained at the output terminal of the inverter circuit composed of the transistors Q_(L1) and Q_(D1) remain at a level V_(C) which is lower than the threshold voltage V_(T), even when the gate terminal of the load transistor Q_(L1) receives a voltage V_(A) higher than the threshold voltage V_(T) while the gate terminal of the driver transistor Q_(D1) receives the synchronizing pulse φ₂ of the voltage level "H" higher than the threshold voltage V_(T).

At a moment t₂, the level of the synchronizing pulse φ₂ is changed to "L" so that the driver transistor Q_(D1) is turned off with the result that the voltage V₀₁ at the output terminal is raised due to the supply of the drain current from the load transistor Q_(L1). Partly because of the rise of the output terminal voltage V₀₁ and partly because of the operation of the feedback capacitor C_(F), the voltage V₁ at the gate terminal of the load transistor Q_(L1) is incremented by ΔV₁ which is given by the following formula (6). ##EQU3## where, V₀₁ represents the voltage obtained at the output terminal when the voltage V₁ (.tbd.V_(B)) after the increment of the voltage is applied to the gate terminal of the load transistor Q_(L1).

It is possible to obtain the condition V₀₁ (V₁ =V_(B))= V_(DD), by making the capacitance of the feedback capacitor C_(F) to be suitably greater than the parasitic capacitance C_(S) connected to the gate terminal of the load transistor Q_(L1). The manner in which the voltage at the gate terminal of the load transistor Q_(L1) rises is the same as that in the bootstrap inverter explained before in connection with FIGS. 2A and 2B.

The voltage V₀₁ derived from the output terminal of the first stage is held at the "H" level for the period between the moment t₂ and a moment t₃ so that the biasing MOS transistor Q_(B2) of the second-stage basic circuit 21₋₂ receiving this output voltage V₀₁ is held on. As a result, the source terminal voltage V₂ of the transistor Q_(B2) is raised and set at the voltage V_(A) and this voltage V_(A) is maintained even after the moment t₃.

At the moment T₃, the driver transistor Q_(D1) of the first-stage basic circuit 21₋₁ is turned on because the synchronizing pulse φ₂ is switched to "H" level at this moment. As a result, the output terminal voltage V₀₁ starts to fall. In consequence, the drain terminal voltage V₁ of the MOS transistor Q_(R1) of the first-stage basic circuit 21₁ tends to come down. Simultaneously with the start of the fall of the output terminal voltage V₀₁ or, alternatively, after the elapse of a predetermined time from the moment of the start of the fall of the output terminal voltage, the synchronizing pulse φ₄ is switched to "H" level so that the MOS transistor Q_(R1) is turned on, whereby the voltage V₁ is forcibly reduced to the level of the ground potential. This in turn causes the load transistor Q_(L1) to be turned off so that the output terminal voltage V₀₁ is lowered to the ground potential.

At the moment t₂, the output terminal voltage V₀₁ of the first-stage basic circuit 21₋₁, now switched to "H" level, is input so that the second-stage basic circuit 21₋₂, in which the source terminal voltage V₂ of the MOS type transistor Q_(B2) has been set at V_(A), operates in accordance with the timing of the synchronizing pulses φ₁ and φ₃ in the chart of FIG. 3B, in the same manner as the first-stage basic circuit 21₋₁. That is, the second-stage basic circuit 21₋₂ produces an output voltage V₀₂ of the same level as the source voltage V_(DD) at a moment t₄ at which the synchronizing pulse φ₁ is switched to "L" level, as will be seen from FIG. 3B.

In this manner, output voltages V₀₃, . . . are successively output from the output terminals 22₋₃ . . . of the basic circuits 21₋₃ . . . of the successive stages, in the period t_(p) between the moment at which the synchronizing pulse φ₂ falls and the moment at which the synchronizing pulse φ₁ falls.

FIG. 4 shows the circuit arrangement used in a second embodiment of the present invention. In this Figure, the same reference numerals are used to denote the same parts or members as those used in the first embodiment shown in FIG. 3A. The circuit arrangement in the second embodiment is materially the same as that of the first embodiment except that the drain terminals of the third MOS transistors Q_(B1), Q_(B2) . . . of the basic circuits 21₋₁, 21₋₂ . . . of the successive stages are commonly connected to the gate terminals. Timings and waveforms of the operating pulses, as well as the voltage waveforms in various portions of the circuit, are identical to those in the first embodiment explained before in connection with FIG. 3B.

In this embodiment, the supply of the drain currents of the MOS transistors Q_(B1), Q_(B2), . . . is conducted via the juncture of the gate terminal rather than from the source voltages V_(DD), so that the high-speed operation characteristic is somewhat impaired, although the overall performance is materially equivalent to that of the first embodiment. Moreover, the second embodiment offers an advantage in that the wiring area for the elements can be appreciably reduced as compared with the first embodiment.

FIG. 5A shows the circuit arrangement in a third embodiment of the present invention. This third embodiment is intended for further reducing the number of elements constituting each basic circuit. A first-stage basic circuit 31₋₁ has three MOS transistors Q_(D1), Q_(L1), Q_(T1) and a capacitor C_(F). The MOS transistors Q_(D1), Q_(L1), Q_(T1) perform functions equivalent to those performed by the MOS transistors Q₁, Q₂, Q₃ of the bootstrap inverter explained before in connection with FIG. 2A. The MOS transistors Q_(D1) and Q_(L1) which are connected in series to each other constitute an inverter circuit in which the transistor Q_(L1) serves as a load transistor while the transistor Q_(D1) functions as a driver transistor. This inverter circuit is connected between the power supply V_(DD) and the grounding terminal. The capacitor C_(F) also is constituted by a MOS diode and corresponds to the feedback capacitor C₁ of the bootstrap inverter shown in FIG. 2A. The capacitor C_(F) is connected between the gate terminal of the MOS transistor Q_(L1) and the point of juncture between the MOS transistors Q_(D1) and Q_(L1). A symbol C_(S) represents a parasitic capacitance corresponding to the parasitic capacitance C₂.

The source electrode of the MOS transistor Q_(T1) is connected to the gate terminal of the load transistor Q_(L1). The drain terminal of the transistor Q_(T1) receives the start pulse ST while the gate terminal of the same receives the transfer synchronizing pulse φ₃. On the other hand, the gate terminal of the driver transistor Q_(D1) receives the synchronizing pulse φ₂ and the point of juncture between the MOS transistors Q_(D1) and Q_(L1) constituting the inverter circuit constitutes an output terminal 32₋₁.

A second-stage basic circuit 31₋₂ has a construction which is substantially the same as the first-stage basic circuit 31₋₁ except that it receives different synchronizing pulses. Thus, the second-stage basic circuit 31₋₂ comprises MOS transistors Q_(D2), Q_(L2) and Q_(T2) corresponding to the MOS transistors Q_(D1), Q_(L1) and Q_(T1) of the first-stage basic circuit 31₋₁, a feedback capacitor C_(F) and a parasitic capacitance C_(s). The output terminal 32₋₁ of the first-stage basic circuit 31₋₁ is connected to the drain terminal of the MOS transistor Q_(T2) so that the output from the first-stage basic circuit 31₋₁ is input to the second-stage basic circuit 31₋₂. The gate terminal of the driver transistor Q_(D2) and the gate terminal of the MOS transistor Q_(T2) receive synchronizing pulses φ₁ and φ₄, respectively. The first- and second-stage basic circuits 31₋₁ and 31₋₂ are alternately connected in a multiplicity of stages, thus constituting a scanning pulse generating circuit of the present invention. The operation of this scanning pulse generating circuit will be described with reference to FIG. 5B, which shows waveforms of pulses applied to various portions of the circuit and waveforms of voltages obtained at various portions of the circuit. The following description is based upon an assumption that all the MOS transistors employed in the scanning pulse generating circuit are of the N-channel type.

At a moment t₁, the start pulse ST applied to the drain terminal of the MOS transistor Q_(T1) of the first-stage basic circuit 31₋₁ is switched to "H" level. At the same time, the synchronizing pulse (transfer pulse) φ₃ applied to the gate terminal of the MOS transistor Q_(T1) is switched to "H" level, whereby the MOS transistor Q_(T1) is turned on. In consequence, the voltage V₁ at the node 41 to which the source terminal of the MOS transistor Q_(T1) is connected is raised to V_(A). The source terminal voltage V₁ in this state is given by the following formula (7).

    V.sub.1 =V.sub.A .tbd.V(H) -V.sub.T -ΔV.sub.T        (7)

where, V(H) represents the voltage of the "H" level of the start pulse ST shown in FIG. 5B. A symbol V_(T) represents the threshold voltage of the MOS transistor Q_(T1). Amount ΔV_(T) of dropping of the voltage due to substrate effect is expressed by the following formula (8). ##EQU4## where, K is a value given by ##EQU5##

When a voltage V₁ which is equal to V_(A) is applied to the gate terminal of the load transistor Q_(L1), the transistor Q_(L1) is switched on. Meanwhile, the driver transistor Q_(D1) has already been turned on because its gate terminal receives the synchronizing pulse φ₂ the level of which has already been changed to "H", so that the output terminal voltage V₀₁ of the first-stage basic circuit is held at the low level of V₀₁ ("L")=V_(c) (<V_(T)). This voltage V_(C) corresponds to the "L" level of the output voltage V_(OUT) of the bootstrap inverter explained before in connection with FIGS. 2A and 2B, and can materially be determined by the following equation:

    [g.sub.m (Q.sub.L1)/g.sub.m (Q.sub.D1)]×V.sub.DD

where, g_(m) (Q_(D1)) and g_(m) (Q_(L1)) represent the conductance values of the driver transistor Q_(D1) and the load transistor Q_(L1) which in cooperation constitute an inverter circuit.

At a moment T₂, the level of the synchronizing pulse φ₂ is switched to "L" level so that the driver transistor Q_(D1) is turned off. In this state, the voltage V₁ at the node 41 is held at the same level as the voltage V₁ (t₁) obtained at the moment T₁ so that the load transistor Q_(L1) is held in on state, whereby the voltage V₀₁ at the output terminal rises.

Then, the first stage basic circuit operates in accordance with the operation principle of the bootstrap inverter explained before in connection with FIGS. 2A and 2B. Namely, the voltage at the gate terminal of the load transistor Q_(L1) is raised as a result of the rise of the output terminal voltage V₀₁ and the operation of the feedback capacitor C_(F), so that a voltage V₁ (t₂) as represented by the following formula (9) is obtained at the node 41. ##EQU6## where, V₀₁ represents the output voltage which is obtained when the voltage V₁ (=V_(B)) at the node 41 after the rise is supplied to the gate terminal of the load transistor Q_(L1).

By selecting the capacitance of the feedback capacitor C_(f) to be suitably greater than the parasitic capacitance C_(S) connected to the gate terminal of the load transistor Q_(L1), it is possible to obtain the following conditions.

    V.sub.01 (V.sub.1 =V.sub.B)=V.sub.DD

The output terminal voltage V₀₁ of the first-stage basic circuit 31₋₁ is maintained at "H" level, i.e., at the same level as the source voltage V_(DD), over a period between the moment t₂ and a moment t₃ at which the synchronizing pulse φ₂ is switched to "H" level. At the moment t₂, the synchronizing pulse φ₄ has been set at "H" level so that the MOS transistor Q_(T2) of the second-stage basic circuit 31₋₂ has been turned on. In consequence, the output voltage V₀₁ (=V_(DD)) of the first-stage basic circuit 31₋₁ is transmitted to the source terminal of the transistor Q_(T2), whereby the voltage at the node 42 is changed to V₂ (t₂). The value of this voltage V₂ (t₂) equals the voltage V₁ (t₁)=V_(A) unless the threshold voltage V_(T) of the MOS transistor Q_(T1) and the MOS transistor Q_(T2) is changed. This value of the voltage V₂ (t₂) is maintained even after the moment T₃.

At the moment t₃, the synchronizing pulse φ₂ is switched to "H" level so that the driver transistor Q_(D1) is turned on, with the result that the output terminal voltage V₀₁ starts to fall to a level V₀₁ (t₃)=V_(C), so that the voltage V₁ at the node 41 of the first-stage basic circuit 31₋₁ is lowered to the level V_(A). Subsequently, at a moment t₄, the start pulse ST is switched to "H" level while the synchronizing pulse φ₃ is switched to "H" level, whereby the source terminal of the MOS transistor Q_(T1) is switched to "L" level with the result that both the voltage V₁ (t₄) at the node 41 and the output teminal voltage V₀₁ (t₄) are reduced to the grounding level.

The second-stage basic circuit 31₋₂ receives the output terminal voltage V₀₁ of the first-stage basic circuit 31₋₁ which was set at "H" level at the moment t₂. At the same time, the voltage V₂ (t₂) at the node 42 is set at V_(A). The second-stage basic circuit 31₋₂ therefore performs the same operation as the operation of the first-stage basic circuit 31₋₁ in accordance with the synchronizing pulses φ₁ and φ₄ the waveforms and timing of which are shown in FIG. 5B, so that an output voltage V₀₂ (=V_(DD)) of "H" level is obtained from the output terminal 32₋₂ thereof at the moment t₅ at which synchronizing pulse φ₁ is switched to "L" level. Thereafter, the base circuits 31₋₃, . . . of the third and subsequent stages operate in the same manners as those described in accordance with the synchronizing pulses φ₁ to φ₄ shown in FIG. 5B, so that output voltages of "H" level which is equal to V_(DD) are successively derived from the output terminals 32₋₂, . . . in a successively-shifted manner with a period T_(P) which is equal to the length of time between the moment at which the synchronizing pulse φ₂ falls and the moment at which the synchronizing pulse φ₁ falls.

In the chart shown in FIG. 5B, the mesial magnitude time width Δt between the rise of the synchronizing pulse φ₃ and the fall of the synchronizing pulse φ₁, and the mesial magnitude time Δt between the rise of the synchronizing pulse φ₄ and the fall of the synchronizing pulse φ₂ are determined to meet the condition of Δt=0. This, however, is not essential and the substantially same effect can be obtained even under the condition of Δt=0.

In the embodiments described hereinbefore, the outputs from the output terminals of the basic circuits of the successive stages are used as the scanning pulses. The "L" level of the output voltages from the respective output terminals are determined by the "H" level of the synchronizing pulses φ₁ and φ₂ so that there is a risk that fluctuation may occur in the "L" level of every other output voltages due to difference in the "H" level between the synchronizing pulses φ₁ and φ₂. In order to obviate such a fluctuation, it is advisable to arrange such that only the outputs from the group of basic circuits driven by the synchronizing pulse φ₁ or the group of basic circuits driven by the other synchronizing pulse φ₂ are used as the scanning pulses.

As will be understood from the foregoing description, the present invention offers the following advantages.

(1) The "H" level of the outputs from the basic circuits of the respective stages of the scanning pulse generating circuit can be maintained substantially constant at the level of the source voltage V_(DD) without being affected by variable factors or parameters such as the threshold voltage V_(T) of the MOS transistor.

(2) The output voltage exhibits no drop at all with respect to the clock voltage and the power supply voltage, by virtue of the booster-type bootstrap effect produced by the bootstrap inverter, so that the scanning pulse generating circuit can be driven at a compareatively low driving voltage.

(3) Although the scanning pulse generating circuit of the invention is of inverter type or ratio type, the power consumption is almost constant regardless of the number of stages of the basic circuit, because only one stage conducts the inverting operation to consume the electrical power at any time during the operation of the scanning pulse generating circuit. This advantage becomes more appreciable as the number of stages of the scanning pulse generating circuit is increased.

(4) The number of elements to be employed in each basic circuit is as small as three to four, so that the wiring space can be saved. This in turn contributes to a reduction in the pitch or spacing between the basic circuits of adjacent stages, thus realizing a higher scale of integration of the circuit.

When the scanning pulse generating circuit of the present invention is applied to a solid-state imaging device, it is possible to eliminate any fixed pattern noise attributable to the operation of the scanning pulse generating circuit, by virtue of the advantage (1) explained above. In addition, the advantage (4) explained above makes it possible to design and construct solid-state imaging devices having higher scale of integration and employing a greater number of pixels. It is also possible to suppress generation of heat in the regions around the pixel arrays by virtue of the advantage (3) and, hence, to eliminate increase in the level of dark outputs from the pixel arrays. 

What is claimed is:
 1. A scanning pulse generating circuit comprising:(a) a plurality of first basic circuits each including:a first MOS transistor with the gate terminal thereof serving as an input terminal; a second MOS transistor connected in series to said first MOS transistor with one of main electrodes thereof being grounded while the gate terminal thereof being capable of receiving a first synchronizing pulse; a third MOS transistor having the gate terminal therof connected to the point of juncture between said first and second MOS transistors while one of the main electrodes thereof being connected to a power supply; a fourth MOS transistor connected in series to said third MOS transistor with one of the main electrodes thereof being grounded while the gate electrode thereof being capable of receiving a second synchronizing pulse; and a first capacitive element connected between the point of juncture between said first and second MOS transistors and the point of juncture between said third and fourth MOS transistors, the point of juncture between said third and fourth MOS transistors constituting an output terminal; and (b) a plurality of second basic circuits each including:fifth, sixth, seventh and eighth MOS transistors corresponding to said first, second, third and fourth MOS transistors of said first basic circuit, respectively; and a second capacitive element corresponding to said first capacitive element; said fifth, sixth, seventh and eighth MOS transistors and said second capacitive element being connected in the same manner as the corresponding elements in said first basic circuit, said output terminal of said first basic circuit being connected to the gate terminal of said fifth MOS transistor, the gate terminals of said sixth and eighth MOS transistors being capable of receiving third and fourth synchronizing pulses, respectively; said first and second basic circuits being connected alternately in a multiplicity of stages so that scanning pulses are derived from the output terminals of said basic circuits of the successive stages.
 2. A scanning pulse generating circuit as set forth in claim 1, wherein the other of said main electrodes of said first MOS transistor of said first basic circuit and the other of said main electrodes of said fifth MOS transistor of said second basic circuit are respectively connected to said power supply.
 3. A scaning pulse generating circuit as set forth in claim 1, wherein the other of said main electrodes of said first MOS transistor of said first basic circuit and the other of said main electrodes of said fifth MOS transistor of said second basic circuit are connected to the gate terminals of the respective MOS transistors.
 4. A scanning pulse generating circuit as set forth in claim 1, wherein each of said first and second capacitive elements are constituted by a MOS diode.
 5. A scanning pulse generating circuit as set forth in claim 2, wherein each of said first and second capacitive elements are constituted by a MOS diode.
 6. A scanning pulse generating circuit as set forth in claim 3, wherein each of said first and second capacitive elements are constituted by a MOS diode.
 7. A scanning pulse generating circuit as set forth in claim 1, wherein only the outputs from the group of said first basic circuits or the outputs from the group of said second basic circuits are used as the scanning pulses.
 8. A scanning pulse generating circuit comprising:(a) a plurality of first basic circuit each including:a first MOS transistor having an input terminal constituted by one of the main electrodes thereof while the gate terminal thereof being capable of receiving a first synchronizing pulse; a second MOS transistor with the gate terminal thereof connected to the other of the main electrodes of said first MOS transistor and with one of the main electrodes thereof connected to a power supply; a third MOS transistor connected in series to said second MOS transistor with one of the main electrodes thereof being grounded while the gate terminal thereof is capable of receiving a second synchronizing pulse; and a first capacitive element connected between said gate terminal of said second MOS transistor and the point of juncture between said second and third MOS transistors, said point of juncture between said second and third MOS transistors serving as an output terminal; and (b) a plurality of second basic circuits each including:fourth, fifth and sixth MOS transistors corresponding to said first, second and third MOS transistors of said first basic circuit, respectively; and a second capacitive element corresponding to said first capacitive element of said first basic circuit; said fourth, fifth and sixth MOS transistors and said second capacitive element being connected in the same manner as the corresponding elements of said first basic circuit, said output terminal of said first basic circuit being connected to one of the main electrodes of said fourth MOS transistor, the gate terminals of said fourth and sixth MOS transistors being capable of receiving third and fourth synchronizing pulses, respectively; said first and second basic circuits being connected alternatingly in a multiplicity of stages so that scanning pulses are successively output from said output terminals of said basic circuits of the successive stages.
 9. A scanning pulse generating circuit as set forth in claim 8, wherein each of said first and second capacitive elements is constituted by a MOS diode.
 10. A scanning pulse generating circuit as set forth in claim 8, wherein only the outputs from the group of said first basic circuits or the outputs from the group of said second basic circuits are used as the scanning pulses. 